1. Field of the Invention
The present invention relates to semiconductor memory devices. More particularly, the present invention relates to a layout structure for a dynamic random access memory (DRAM) in which bit line equalization transistors are provided with a bit line equalization voltage.
2. Description of the Related Art
In order to facilitate the fabrication of DRAMs, an effort has been continuously made to decrease the core and peripheral circuit regions provided with the memory cells and bit line sense amplifiers. For example and with reference to FIGS. 1 and 2, a conventional DRAM provided with stack memory cells, which consist of a storage poly and plate poly stacked over a semiconductor substrate, has a large offset between a cell array region 10 and a region 20 comprising bit line equalization transistors. This relationship makes it very difficult to form an active metal contact 21 to electrically connect metal line VBL(M1) and the active region 30 in order to supply a bit line equalization voltage VBL to bit line equalization regions 20 connected to the active region 30. In order to cope with this difficulty, plate poly 22 is extended to the edge of cell array region 10, as shown in FIG. 2, while the bit line transistors are arranged in bit line equalization region 20 and are separated from an edge of plate poly 22 by a space L. Metal contact 21 is then formed between metal line VBL(M1) and active region 30 to supply bit line equalization voltage VBL to the bit line equalization transistors.
However, since there exists a large offset between cell array region 10 and region 20 comprising the bit line equalization transistors, the metal contact 21 between the metal line VBL(M1) and an active n+region of the bit line equalization transistors is formed at a great distance from cell array region 10. This increases chip size. In fact, metal contact 21 becomes the bottle-neck of the overall metal-active (n.sup.+ or p.sup.+) contact process in the DRAM fabrication process, thus, increasing the size of the metal-active contact of the other regions so that the minimum distance between the metal-active contact and the gate must be increased in most of the transistors in the peripheral regions. Chip size necessarily increases.
Accordingly, the bit line equalization region 20 is a very critical place to design metal-active contacts in the DRAM. In addition, the metal-active contact between all the bit line equalization transistors and the metal line VBL(M1) supplying bit line equalization voltage VBL to the bit line equalization region 20 generates a contact overlap so as to reduce the metal line space, adversely affecting the metal line bridge margin, for example, the margins between active region 30 and plate poly 22, and active region 30 and the equalization metal line VBL(M1).